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g52185-0, rev 4.0 vitesse semiconductor corporation page 1 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery features general description the vsc8114 is an atm/sonet/sdh compatible transceiver integrating an on-chip clock multiplication unit (pll) for high speed clock generation as well as a clock and data recovery unit (cru) with 8-bit serial- to-parallel and parallel-to-serial data conversion. the pll clock is used for serialization in the transmit direc- tion (mux). the recovered clock is used for deserialization in the receive direction (demux). the demultiplexer contains sonet/sdh frame detection and recovery. in addition, the device provides both facility and equip- ment loopback modes and a loop time mode. the part is packaged in a 100pqfp with an integrated heat spreader for optimum thermal performance and reduced cost. the vsc8114 provides an integrated solution for atm physical layers and sonet/sdh systems applications. functional description the vsc8114 is designed to provide a sonet/sdh compliant interface between the high speed optical networks and the lower speed user network interface devices such as the pm5355 s/uni-622. the vsc8114 converts 8 bit parallel data at 77.76mb/s to a serial bit stream at 622.08mb/s. the device also provides a facility loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly to the high speed transmit outputs. a clock multiplier unit (cmu) is integrated into the transmit circuit to gen- erate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76 mhz. the cmu can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing the entire part to a single clock. the block diagram on page 2 shows the major functional blocks associated with the vsc8114. the receive section provides the serial-to-parallel conversion, converting 622mb/s bit stream to an 8 bit par- allel output at 77.76mhz. a clock recovery unit (cru) is integrated into the receive circuit to recover the high speed clock from the received serial data stream. the receive section provides an equipment loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out- puts. the vsc8114 also provides the option of selecting between either its internal crus clock and data sig- nals, or optics containing a cru clock and data signals. the receive section also contains a sonet/sdh frame ? loss of signal (los) input & los detection ? +3.3v/5v programmable pecl serial interface ? provides equipment, facilities and split loop- back modes as well as loop timing mode ? provide pecl reference clock inputs ? meets bellcore, itu and ansi specifications for jitter performance ? low power - 0.9watts typical ? 100 pqfp package ? operates at sts-12/stm-4 (622.08mb/s) data rate ? compatible with industry atm uni devices ? on chip clock generation of the 622.08mhz high speed clock (mux) ? on chip clock recovery of the 622.08mhz high speed clock (demux) ? 8-bit parallel ttl interface with parity error detection and generation ? sonet/sdh frame recovery
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 2 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 detector circuit which is used to provide frame pluses during the a1, a2 boundary in the serial to parallel con- verter. this only occurs when oof is high. both internal and external los functions are supported. the vsc8114 provides the parity error detection and generation for the 8 bit data bus. on the receive side, the parity of the 8 bit data outputs is generated. on the transmit side, the parity of the 8 bit data input is calcu- lated and compared with the received parity input. vsc8114 block diagram transmit section byte-wide data is presented to txin[7:0] and is clocked into the part on the rising edge of txlsckin. see figure 1. the data is then serialized (msb leading) and presented to the txdataout+/- pins. the serial output stream is synchronized to the cmu generated clock which is a phase locked and frequency scaled ver- dq 0 1 0 1 d q 0 1 0 1 8 rxout[7:0] rxlsckout fp oof equloop txdataout+/- 8 txin[7:0] txlsckout txlsckin facloop cmu divide-by-8 1:8 demux framer divide-by-8 8:1 mux parity/ cru rxdatain+/- rxclkin+/- dsblcru 0 1 0 1 1 0 losdet refclkp+/- losdeten_ rec-data rec-clk refsel parity chk reg txinp txperr rxoutp reg losttl lospecl 0 1 looptim0 1 0 crurefsel crurefclk 0 1 crueqlp reset
g52185-0, rev 4.0 vitesse semiconductor corporation page 3 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery sion of the input reference clock. external control input refsel selects the multiply ratio of the cmu (see table 11). a divide-by-8 version of the cmu clock (txlsckout) should be used to synchronize the transmit interface of the uni device to the transmit input registers on the vsc8114 (see application notes, p. 20). figure 1: data and clock transmit block diagram receive section high speed non-return to zero (nrz) serial data at 622mb/s are received by the rxdatain inputs. the cru recovers the high speed clock from the serial data input. the serial data is converted to byte-wide parallel data and presented on rxout[7:0] pins. a divide-by-8 version of the high-speed clock (rxlsckout) should be used to synchronize the byte-serial rxout[7:0] data with the receive portion of the uni device. the on-chip cru is by-passed by setting the dsblcru input high. in this mode, the serial input data and corre- sponding clock are received by the rxdatain and rxclkin inputs respectively. rxdatain is clocked in on the rising edge of rxclkin+. see figure 2. the receive section also includes frame detection and recovery circuitry which detects the sonet/sdh frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on fp coincident with the byte aligned data. the frame recovery is initiated when oof is held high which must occur at least 4 byte clock cycles before the a1a2 boundary. the oof input control is a level-sensitive signal, and the vsc8114 will con- tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. frame detection and recovery occurs when a series of three a1 bytes followed by three a2 bytes has been detected. the parallel output data on rxout[7:0] will be byte aligned starting on the third a2 byte. when a frame is detected, a single byte clock period long pulse is generated on fp which is synchronized with the byte-aligned third a2 byte on rxout[7:0]. the frame detector sends an fp pulse only if oof is high. loss of signal the vsc8114 features loss of signal (los) detection. loss of signal is detected if the incoming serial data stream has no transition continuously for more than 128 bits. during an los condition, the vsc8114 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. the receive section continues to be clocked by the cru as it is now locked to the crurefclk unless dsblcru is active, in which case it will be clocked by the cmu. this los condition will be removed when the part detects more than 16 transitions in a 128 bit time window. this los detection feature can be dis- abled by applying a high level to the losdeten_ input. the vsc8114 also has a ttl input losttl and a d q d q divide-by-8 cmu d q txin[7:0] txlsckin txlsckout txdataout+ txdataout- refclk vsc8114 pm5355
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 4 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 pecl input lospecl to force the part into a loss of signal state. most optics have a pecl output usually called sd or flag indicating the presence or lack of optical power. depending on the optics manufacturer this signal is either active high or active low. the losttl and lospecl inputs are xnord to generate an internal los control signal. see figure 2. the optics sd output should be connected to lospecl. the losttl input should be tied to low if the optics sd is active high. if its active low tie losttl to a high. the inverse is true if the optics use flag for loss of signal figure 2: data and clock receive block diagram facility loopback the facility loopback function is controlled by the facloop signal. when the facloop signal is set high, the facility loopback mode is activated and the high speed serial receive data (rxdatain) is presented to the high speed transmit output (txdataout). see figure 3. in facility loopback mode the high speed receive data (rxdatain) is also converted to parallel data and presented to the low speed receive data output pins (rxout[7:0]). the receive clock (rxclkin) is also divided down and presented to the low speed clock output (rxlsckout). figure 3: facility loopback data path dq dq dq 0 1 divide-by-8 cmu dq pm5355 dq rxout[7:0] fp rxlsckout vsc8114 cru rxdatain+/- rxclkin+/- dsblcru 0 1 0 1 losdeten_ losttl lospecl losdet d q d q 1:8 serial to parallel q d rxdatain txdataout rxout[7:0] q d txin[7:0] 8:1 parallel to serial pll 0 1 0 1 cru facloop rxclkin 0 1 recovered clock
g52185-0, rev 4.0 vitesse semiconductor corporation page 5 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery equipment loopback the equipment loopback function is controlled by the equloop signal. when the equloop signal is set high, the equipment loopback mode is activated and the high speed transmit data generated from the paral- lel to serial conversion of the low speed data (txin[7:0]) is selected and converted back to parallel data in the receiver section and presented to the low speed parallel outputs (rxout[7:0]). see figure 4. the internally generated 622mhz clock is used to generate the low speed receive clock output (rxlsckout). in equipment loopback mode the transmit data (txin[7:0]) is serialized and presented to the high speed output (txdataout) using the clock generated by the on-chip clock multiplier unit. cru equipment loopback exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the way back to the high speed i/o. when the crueqlp signal is set high, transmit data is looped back to the cru, replacing rxdatain figure 4: equipment loopback data path split loopback equipment and facility loopback modes can be enabled simultaneously. in this case, high-speed serial data received (rxdatain) is muxd through to the high-speed serial outputs (txdataout). the low-speed trans- mit byte-wide bus (txin[7:0]) and (txlsckin) is muxd into the low-speed byte-wide receive output bus (rxout[7:0]) and (rxlsckout). see figure 5. figure 5: split loopback datapath d q d q 1:8 serial to parallel q d rxdatain txdataout rxout[7:0] q d 8:1 parallel to serial txin[7:0] ? 8 pll ? 8 rxlsckout txlsckin txlsckout 0 1 equloop d q d q 1:8 serial to parallel q d rxdatain txdataout rxout[7:0] q d 8:1 parallel to serial txin[[7:0] 0 1 cru rxclkin txlsckin rxlsckout dsblcru recovered clock
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 6 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 loop timing looptim0 mode bypasses the cmu when the looptim0 input is asserted high. in this mode the cmu is bypassed by using the receive clock (rxclkin), and the entire part is synchronously clocked from a single external source. parity an even parity input (txinp) is provided for the byte-wide transmit data. this input, along with byte-wide data, is clocked into the vsc8114 on the rising edge of txlsckin. parity is calculated on the clocked in byte- wide data and compared to the clocked in parity input. a parity error is reported on the next txlsckin rising edge on txperr. for no parity errors to result, txinp must be logic 1 when on an odd number of bits in the txin[7:0] are logic 1; otherwise, it must be logic 0. even parity is calculated and clocked out along with byte-wide receive data (rxout[7:0]) on rxoutp. rxoutp is a logic 1 when an odd number of bits on rxout[7:0] are logic 1; ohterwise, it is logic 0. clock synthesis the vsc8114 uses an integrated phase-locked loop (pll) for clock synthesis of the 622mhz high speed clock used for serialization in the transmitter section. the pll is comprised of a phase-frequency detector (pfd), an integrating operation amplifier and a voltage controlled oscillator (vco) configured in classic feed- back system. the pfd compares the selected divided down version of the 622mhz vco (select pin refsel selects divide-by ratios of 8 and 32, see table 11) and the reference clock. the integrator provides a transfer function between input phase error and output voltage control. the vco portion of the pll is a voltage con- trolled ring-oscillator with a center frequency of 622mhz. the reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier through the cp1, cp2, cn1 and cn2 pins. the configuration of these external surface mounted capacitors is shown in figure 6. table 1 shows the recommended external capacitor values for the configurable reference frequencies. good analog design practices should be applied to the board design for these external components. tightly controlled analog ground and power planes should be provided for the pll portion of the circuitry. the dedi- cated pll power (vddana) and ground (vssana) pins should have quiet supply planes to minimize jitter generation within the clock synthesis unit. this is accomplished by either using a ferrite bead or a c-l-c choke ( p filter) on the (vddana) power pins. note: vitesse recommends a ( p filter) c-l-c choke over using a ferrite bead. all ground planes should be tied together using multiple vias. reference clocks note that the cmu uses a differential pecl reference clock input to achieve optimum jitter performance. the cru has the option of either using the cmus reference clock or its own independent reference clock crurefclk. this is accomplished with the control signal crurefsel. the crurefclk should be used if the system is being operated in either a regeneration or loop timing mode. in either of these modes the quality of the crurefclk is not a concern, thus it can be driven by a simple 77.76mhz crystal, the key is its indepen- dence from the cmus reference clock.
g52185-0, rev 4.0 vitesse semiconductor corporation page 7 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery figure 6: external integrator capacitor table 1: recommended external capacitor values clock recovery the fully monolithic clock recovery unit (cru) consists of a phase detector, a frequency detector, a loop filter and a voltage controlled oscillator (vco). the phase detector compares the phase information of the incoming data with the recovered clock. the frequency detector compares the frequency component of the data input with the recovered clock to provide the pull in energy during lock acquisition. the loop filter inte- grates the phase information from the phase and frequency detectors and provides the control voltage to the vco. jitter tolerance jitter tolerance is the ability of the clock recovery unit to track timing variations in the received data stream. the bellcore and itu specifications allow the received optical data to contain jitter. the amount that must be tolerated is a function of the frequency of the jitter. the cru is designed to tolerate jitter with margin over the specification limits, see figure 7. the cru obtains and maintains lock based on the data transition information. when there is no transition on the data stream, the recovered clock frequency can drift. the vsc8114 can maintain lock over 100 bits of no switching on the data stream. reference frequency [mhz] divide ratio cp cn type size tol. 19.44 32 0.1 0.1 x7r 0603/0803 +/-10% 77.76 8 0.1 0.1 x7r 0603/0803 +/-10% + - cp1 cp2 cn1 cn2 cp = 0.1 m f cn = 0.1 m f
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 8 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 figure 7: jitter tolerance data latency the vsc8114 contains several operating modes, each of which exercise different logic paths through the part. table 2 bounds the data latency through each path with an associated clock signal. table 2: data latency circuit mode description clock reference range of clock cycles receive msb at rxdatain to data on rxout [7:0] rxclkin 25-35 facilities loopback msb at rxdatain to msb at txdataout rxclkin 2-4 10 30 300 25 k 250 k 15 1.5 0.15 j itter f req (h z ) j itter (ui p - p ) 2.5m 150 60 6 0.6 bellcore requirement vsc8114 guaranteed jitter tolerance
g52185-0, rev 4.0 vitesse semiconductor corporation page 9 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery ac timing characteristics figure 8: receive high speed data input timing diagram table 3: receive high speed data input timing table figure 9: receive data output timing diagram table 4: receive data output timing table parameter description min typ max units t rxclk receive clock period - 1.608 - ns t rxsu serial data setup time with respect to rxclkin 250 - - ps t rxh serial data hold time with respect to rxclkin 250 - - ps parameter description min typ max units t rxclkin receive clock period - 1.608 - ns t rxlsck receive data output byte clock period - 12.86 - ns t rxvalid time data on rxout [7:0], fp, and rxoutp is valid before and after the rising edge of rxlsckout 4.0 - - ns t pw pulse width of frame detection pulse fp - 12.86 - ns t rxclk t rxsu t rxh rxclkin+ rxclkin- rxdatain+ rxdatain- a1 a2 a2 a2 a2 t rxvalid t rxlsck t rxclkin rxout [7:0] rxlsckout rxclkin+ rxclkin- fp rxoutp
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 10 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 figure 10: transmit high speed data timing diagram table 5: transmit high speed data timing table figure 11: transmit data timing diagram table 6: transmit data input timing table note: duty cycle for txlsckout is 50% +/- 10% worst case parameter description min typ max units t txdat transmit data width - 1.608 - ns parameter description min typ max units t clkin transmit data input byte clock period - 12.86 - ns t insu transmit data and parity setup time with respect to txlsckin 1.0 - - ns t inh transmit data and parity hold time with respect to txlsckin 1.0 - - ns t prop maximum allowable propagation delay for connecting txlsckout to txlsckin --3.5ns t err propagation delay from txlsckin to txperr 3.2 - 9.0 ns t txdat txdataout+ txdataout- t prop t clkin t insu t inh txlsckout txlsckin txin [7:0] txperr t err txinp
g52185-0, rev 4.0 vitesse semiconductor corporation page 11 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery ac characteristics table 7: pecl and ttl outputs dc characteristics table 8: pecl and ttl inputs and outputs parameter description min typ max units conditions t r,ttl ttl output rise time 2ns 10-90% t f,ttl ttl output fall time 1.5 ns 10-90% t r,pecl pecl output rise time 350 ps 20-80% t f,pecl pecl output fall time 350 ps 20-80% parameter description min typ max units conditions v oh output high voltage (pecl) v ddp C 0.9v v v ol output low voltage (pecl) 0.7 v v ocm o/p common mode range (pecl) 1.1 v ddp C 1.3v v d v out75 differential output voltage (pecl) 600 1300mv 75 w to v ddp C 2.0v d v out50 differential output voltage (pecl) 600 1300mv 50 w to v ddp C 2.0v v ih input high voltage (pecl) v ddp C 0.9v v ddp C 0.3v v for single ended v il input low voltage (pecl) 0v ddp C 1.72v v for single ended d v in differential input voltage (pecl) 400 1600 mv v icm i/p common mode range (pecl) 1.5 C d v in /2 v ddp C 1.0 C d v in /2 v v oh output high voltage (ttl) 2.4 v i oh = -1.0 ma v ol output low voltage (ttl) 0.5 v i ol = +1.0 ma v ih input high voltage (ttl) 2.0 5.5 v
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 12 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 power dissipation table 9: power supply currents absolute maximum ratings (1) power supply voltage ( v dd ) potential to gnd .................................................................................-0.5v to +4v pecl i/o supply voltage ( v ddp ) potential to gnd..........................................................................-0.5v to +6v dc input voltage (pecl inputs).......................................................................................... -0.5v t o v ddp +0.5v dc input voltage (ttl inputs) .................................................................................................. ....... -0.5v to 5.5v dc output voltage (ttl outputs)........................................................................................ -0.5v to v dd + 0.5v output current (ttl outputs) ................................................................................................... .............. +/-50ma output current (pecl outputs).................................................................................................. ..............+/-50ma case temperature under bias .................................................................................................... .....-55 o to +125 o c storage temperature............................................................................................................ ......... -65 o c to +150 o c maximum input esd (human body model)........................................................................................... ... 1500 v note: caution: stresses listed under absolute maximum ratings may be applied to devices one at a time without causing permanent damage. functionality at or exceeding the values listed is not implied. exposure to these values for extended periods may affect device reliability. recommended operating conditions power supply voltage ( v dd ) ................................................................................................................. +3.3v % pecl i/o supply voltage ( v ddp ).......................................................................................... +3.3v or +5.0v % commercial operating temperature range ..................................................................... 0 o ambient to 70 o c case extended operating temperature range.........................................................................0 o ambient to 115 o c case industrial operating temperature range ...................................................................... -40 o ambient to 85 o c case v il input low voltage (ttl) 0 0.8 v i ih input high current (ttl) 50 500 m a 2.0v< v in < 5.5v, typical@2.4v i il input low current (ttl) -500 m a -0.5v< v in <0.8v parameter description max units i dd power supply current from v dd 410 ma i ddp power supply current from pecl i/o supply v ddp (output unloaded) 30 ma p d power dissipation (worst case) (i dd + i ddp ) x 3.45v = 1.51 1.51 w parameter description min typ max units conditions 5 5
g52185-0, rev 4.0 vitesse semiconductor corporation page 13 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery clock recovery unit table 10: reference frequency for the cru clock multiplier unit table 11: reference frequency selection and output frequency control table 12: clock multiplier unit performance (1) these reference clock jitter limits are required for the outputs to meet sonet system level jitter requirements (< 10 muirms) (2) needed to meet sonet output frequency stability requirements (3) measured note: jitter specification is defined utilizing a 12khz - 5mhz lp-hp single pole filter. crurefsel refsel crurefclk frequency [mhz] output frequency [mhz] 1x 77.76 500ppm 622.08 0 uses cmus reference clock (see table 11 below) refsel reference frequency [mhz] output frequency [mhz] 1 19.44 622.08 0 77.76 622.08 name description min typ max units rcd reference clock duty cycle 40 60 % rcj reference clock jitter (rms) @ 77.76 mhz ref (1) 13 ps rcj reference clock jitter (rms) @ 19.44 mhz ref (1) 5ps rc f reference clock frequency tolerance (2) -20 +20 ppm ocj txdataout+/- jitter (rms) @ 77.76 mhz ref (3) 8ps ocj txdataout+/- jitter (rms) @ 19.44 mhz ref (3) 15 ps ocf range output frequency (alternating 10 pattern) 620 624 mb/s
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 14 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 package pin description table 13: pin definitions signal pin i/o level pin description facloop 1 i ttl facility loopback, loops high-speed data vdd 2 +3.3v +3.3v power supply crueqlp 3 i ttl cru equipment loopback, loops txdataout to the cru replacing rxdatain+/- reset 4 i ttl resets frame detection, dividers, controls; active high looptim0 5 i ttl enable loop timing operation; active high n/c 6 no connection refsel 7 i ttl reference clock select, refer to table 11 n/c 8 no connection vddp 9 +3.3/+5v +3.3v or +5v power supply for pecl i/os txdataout+ 10 o pecl transmit output, high speed differential data + txdataout- 11 o pecl transmit output, high speed differential data - vss 12 gnd ground n/c 13 no connection n/c 14 no connection vddp 15 +3.3/+5v +3.3v or +5v power supply for pecl i/os n/c 16 no connection losdeten_ 17 i ttl enables internal los detection (active low). vss 18 gnd ground rxclkin+ 19 i pecl receive high speed differential clock input+ rxclkin- 20 i pecl receive high speed differential clock input- vddp 21 +3.3/+5v +3.3v or +5v power supply for pecl i/os oof 22 i ttl out of frame; frame detection initiated with high level dsblcru 23 i ttl disable on-chip clock recovery unit; active high rxdatain+ 24 i pecl receive high speed differential data input+ rxdatain- 25 i pecl receive high speed differential data input- nc 26 no connection nc 27 no connection vdd 28 +3.3v +3.3v power supply refclkp+ 29 i pecl pecl reference clock input+ refclkp- 30 i pecl pecl reference clock input- vdd 31 +3.3v +3.3v power supply
g52185-0, rev 4.0 vitesse semiconductor corporation page 15 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery n/c 32 no connection rxoutp 33 o ttl receive output data even parity vss 34 gnd ground rxout0 35 o ttl receive output data bit0 rxout1 36 o ttl receive output data bit1 vss 37 gnd ground rxout2 38 o ttl receive output data bit2 rxout3 39 o ttl receive output data bit3 vss 40 gnd ground rxout4 41 o ttl receive output data bit4 rxout5 42 o ttl receive output data bit5 vss 43 gnd ground rxout6 44 o ttl receive output data bit6 rxout7 45 o ttl receive output data bit7 vss 46 gnd ground rxlsckout 47 o ttl receive byte clock output fp 48 o ttl frame detection pulse vdd 49 +3.3v +3.3v power supply txperr 50 o ttl transmit input data parity error crurefclk 51 i ttl optional external cru reference clock @ 77.76mhz losttl 52 i ttl loss of signal control - ttl input lospecl 53 i pecl loss of signal control- single ended pecl input vdd 54 +3.3v +3.3v power supply vss 55 gnd ground n/c 56 no connection n/c 57 no connection vdd 58 +3.3v +3.3v power supply vssa 59 gnd analog ground (cmu) vssa 60 gnd analog ground (cmu) n/c 61 no connection vdda 62 +3.3v analog power supply (cmu) cp1 63 analog cmu external capacitor (see figure 6, and table 1) cn1 64 analog cmu external capacitor (see figure 6, and table 1) cn2 65 analog cmu external capacitor (see figure 6, and table 1) signal pin i/o level pin description
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 16 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 cp2 66 analog cmu external capacitor (see figure 6, and table 1) vdda 67 +3.3v analog power supply (cmu) vdda 68 +3.3v analog power supply (cru) vdda 69 +3.3v analog power supply (cru) vssa 70 gnd analog ground (cru) vssa 71 gnd analog ground (cru) vss 72 gnd ground n/c 73 no connection n/c 74 no connection vss 75 gnd ground vdd 76 +3.3v +3.3v power supply n/c 77 no connection n/c 78 no connection n/c 79 no connection n/c 80 no connection vdd 81 +3.3v +3.3v power supply txlsckout 82 o ttl transmit byte clock out txlsckin 83 i ttl transmit byte clock in vss 84 gnd ground txin7 85 i ttl transmit input data bit7 txin6 86 i ttl transmit input data bit6 vss 87 gnd ground txin5 88 i ttl transmit input data bit5 txin4 89 i ttl transmit input data bit4 n/c 90 no connection txin3 91 i ttl transmit input data bit3 txin2 92 i ttl transmit input data bit2 vss 93 gnd ground txin1 94 i ttl transmit input data bit1 txin0 95 i ttl transmit input data bit0 n/c 96 no connection txinp 97 i ttl transmit input data even parity crurefsel 98 i ttl selects between cmus or crus reference clock vdd 99 +3.3v +3.3v power supply equloop 100 i ttl equipment loopback, loops low-speed byte-wide data signal pin i/o level pin description
g52185-0, rev 4.0 vitesse semiconductor corporation page 17 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery package information notes: (1) drawings not to scale. (2) two styles of exposed heat spreaders (3) all units in millimeters unless otherwise noted may be used; square or oval. 100 pqfp package drawings package #: 101-202-4 issue #: 1 r r 1 a a 1 b l 0.25 0.17 max q 6 4 q 2 q 3 e a 2 top view rad 2.92 .50 (2x) 2.54 .50 (2x) pin 100 pin 1 exposed heatsink 9.0 x 9.0 d1 d e1 e (note 2) (n0te 2) (note 2) (note 2) pin 30 pin 50 key mm tolerance a3.40 max a1 0.25 min. a2 2.7 .10 d 17.20 .20 d1 14.00 .10 e 23.20 .20 e1 20.00 .10 l0.80 .2 e 0.65 nom b0.30 .10 q 0 -7 r.30 +0/-.1 r1 .2 nom q2 15 q3 15
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 18 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 the vsc8114 is manufactured in a 100pqfp package which is supplied by two different vendors. the crit- ical dimensions in the drawing represent the superset of dimensions for both packages. the significant differ- ence between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink. package thermal characteristics the vsc8114 is packaged in a thermally enhanced 100pqfp with an embedded heat sink. the heat sink surface configurations are shown in the package drawings. with natural convection, the case to air thermal resis- tance is estimated to be 27.5 o c/w. the air flow versus thermal resistance relationship is shown in table 14. junction to case thermal resistance is 1.2 o c/w table 14: theta case to ambient versus air velocity air velocity (lfpm) case to air thermal resistance o c/w 027.5 100 23.1 200 19.8 400 17.6 600 16
g52185-0, rev 4.0 vitesse semiconductor corporation page 19 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery ordering information the order number for this product are: part number device type VSC8114QB: 622mb/s mux/dmux with cmu and cru in 100 pin pqfp commercial temperature, 0 c ambient to 70 c case VSC8114QB1 622mb/s mux/dmux with cmu and cru in 100 pin pqfp extended temperature, 0 c to 85 c ambient (equivalent to 0 c ambient to 115 c case) VSC8114QB2 622mb/s mux/dmux with cmu and cru in 100 pin pqfp industrial temperature, -40 c ambient to 85 c case notice this document contains preliminary information about a new product in the preproduction phase of devel- opment. the information in this document is based on initial product characterization. vitesse reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availabil- ity of the product at any time. the reader is cautioned to confirm this datasheet is current prior to using it for design . warning vitesse semiconductor corporations product are not intended for use in life support appliances, devices or sys- tems. use of a vitesse product in such applications without the written consent is prohibited.
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 20 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 application notes interconnecting the byte clocks (txlsckout and txlsckin) the byte clock (txlsckout and txlsckin) on the vsc8114 has been brought off-chip to allow as much flexibility in system-level clocking schemes as possible. since the byte clock (txlsckout) clocks both the vsc8114 and the uni devices, it is important to pay close attention to the routing of this signal. the uni device in general is a cmos part which can have very wide spreads in timing (1-11ns clock in to parallel data out for the pm5355), which utilizes most of the 12.86ns period (at 78mhz), leaving little for the trace delays and set-up times required to interconnect the 2 devices. the vsc8114 and the uni device should be placed as close to each other as possible to provide maximum setup and hold time margin at the inputs of the vsc8114. figure 12 suggests two different ways of routing the txlsckout-to-txlsckin clock trace when used in a 622 mhz mode, which ever method is used the trans- mission line trace impedance should be no lower than 75 ohms. figure 12: interconnecting the byte clocks (1) txlsckout and txlsckin are tied together at the pins of the vsc8114. this provides a setup and hold time margin for the txin input of ? t su,margin = t clk - t tclk-pout,max (pm5355) - t su,min (vsc8114) - 2xt trace = 0.86ns - 2xt trace ? t hold,margin = t tclk-pout,min (pm5355) - t hold,min (vsc8114) + 2xt trace = 2xt trace (2) txlsckout is daisy chained to the uni device and then routed back to the vsc8114 along with the byte data. this interface provides a setup and hold time margin for the txin input of ? t su,margin = t clk - t tclk-pout,max (pm5355) - t su,min (vsc8114) = 0.86ns ? t hold,margin = t tclk-pout,min (pm5355) - t hold,min (vsc8114) = 0ns option (2) does not provide any hold time margin, while option (1) requires the one-way trace delay (t trace ) to be less than 0.43ns (~3 inches). the general recommendation is to apply option (1) and place the vsc8114 and pm5355 as close to each other as possible. if the one-way trace delay cannot be kept less than 0.43ns with a 50pf load, daisy-chaining (option 2) should be applied - close attention must be paid to signal routing in this case because of the lack of hold time margin. txin[7:0] txlsckin txlsckout pm5355 vsc8114 (1) (2) pout[7:0] tclk t trace
g52185-0, rev 4.0 vitesse semiconductor corporation page 21 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery important note: the 11 ns max tpd on the pm5355 assumes a 50pf load @ 60ps/pf, therefore 3 ns of the max delay is due to loading. the vsc8114 input (txlsckin) plus package is about 6pf. assuming about 1 pf/ inch of 75 ohm trace on fr4 plus the vsc8114 6pf load, the user would in most cases choose option 1. dc coupling and terminating high-speed pecl i/os the high speed signals on the vsc8114 (rxdatain, rxclkin, txdataout, refclkp, lospecl) use 3.3/5v programmable pecl i/os which can be direct coupled to either +3.3v pecl or +5v pecl signals from the optics. these pecl levels are essentially ecl levels shifted positive by 3.3 volts or 5 volts. these pecl i/os are referenced to the v ddp supply (vddp) and are terminated to ground. to program these i/os for either 3.3v or 5v interface, the 3 v ddp pins (pin 9, 15, 21) are required to connect to 3.3v or 5v supplies accordingly. ac coupling and terminating high-speed pecl i/os if the optics modules provide ecl level interface, the high speed signals can be ac coupled to the vsc8114 as well. the pecl receiver inputs of the vsc8114 are internally biased at vdd/2. therefore, ac- coupling to the vsc8114 inputs is accomplished by providing the pull-down resistor for the open-source pecl output and an ac-coupling capacitor used to eliminate the dc component of the output signal. this capacitor allows the pecl receivers of the vsc8114 to self-bias via its internal resistor divider network (see figure 14). the pecl output drivers are capable of sourcing current but not sinking it. to establish a low output level, a pull-down resistor, traditionally connected to vdd-2.0v, is needed when the output fet is turned off. since vdd-2.0v is usually not present in the system, the resistor should be terminated to ground for conve- nience. the vsc8114 output drivers should be either ac-coupled to the 5.0v pecl inputs of the optics mod- ule, or translated (dc level shift). appropriate biasing techniques for setting the dc-level of these inputs should be employed. the dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in figure 14. the figure shows the appropriate termination values when interfacing 3.3v pecl to 5.0v pecl. this network provides the equivalent 50 ohm termination for the high speed i/os and also provides the required dc biasing for the receivers of the optics module. table 15 contains recommended values for each of the components. ttl input structure the ttl inputs of the vsc8114 are 3.3v ttl which can accept 5.0v ttl levels within a given set of tol- erances (see table 8). the input structure, shown in figure 14, uses a current limiter to avoid overdriving the input fets. initialization the vsc8114 contains a reset caps pin which is only needed for vlsi production test requirements at vitesse. the chip will initialize on its own as data is clocked through the device. the receive section will frame align on the a1, a2 boundary of the incoming sonet/sdh data stream. (see receive section on page 3).
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 22 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99 layout of the high speed signals the routing of the high speed signals should be done using good high speed design practices. this would include using controlled impedance lines and keeping the distance between components to an absolute mini- mum. in addition, stubs should be kept at a minimum as well as any routing discontinuities. this will help min- imize reflections and ringing on the high speed lines and insure the maximum eye opening. in addition the output pull down resistor should be placed as close to the vsc8114 pin as possible while the ac-coupling capacitor and the biasing resistors should be placed as close as possible to the optics input pin. the same is true on the receive circuit side. using small outline components and minimum pad sizes also helps in reducing dis- continuities. ground planes the ground plane for the components used in the high speed interface should be continuous and not sec- tioned in an attempt to provide isolation to various components. sectioning of the ground planes tends to inter- fere with the ground return currents on the signal lines. in addition, the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple. sectioning of the positive supplies can provide some isolation benefits. figure 13: ac coupled high speed i/o table 15: ac coupling component values component val u e tol erance r1 270 ohms 5% r2 75 ohms 5% r3 68 ohms 1% r4 190 ohms 1% c1, c2, c3, c4 .01uf high frequency pc board trace pc board trace driver (optics module) receiver (optics module) vsc8113 pecl i/o r2 r4 c2 c1 r3 note: only one side of a differential signal is shown. r1 gnd +3.3v +5.0v gnd gnd gnd vsc8114
g52185-0, rev 4.0 vitesse semiconductor corporation page 23 11/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation data sheet v sc8114 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery figure 14: input structures input input high speed differential input v ddp gnd +3.3 /+5 v (rxdatain+/rxdatain-) refclk and ttl inputs input +3.3 v current limit gnd v dd r r all resistors 3.3k (rxclkin+/rxclkin-) +3.3 v
vitesse semiconductor corporation data sheet vsc811 4 atm/sonet/sdh 622 mb/s transceiver mux/demux with integrated clock generation and clock recovery page 24 vitesse semiconductor corporation g52185-0, rev 4.0 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 11/1/99

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